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[#61174] Add RISCV_PRIV_UNRATIFIED
1 parent 6e1fd04 commit 2f8dc48

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3 files changed

+9
-3
lines changed

3 files changed

+9
-3
lines changed

arch/riscv/arch_exports.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,7 @@ EXC_INT_1(uint32_t, tlib_is_feature_allowed, uint32_t, feature_bit)
146146

147147
void tlib_set_privilege_architecture(int32_t privilege_architecture)
148148
{
149-
if (privilege_architecture > RISCV_PRIV1_12) {
149+
if (privilege_architecture > RISCV_PRIV1_12 && privilege_architecture != RISCV_PRIV_UNRATIFIED) {
150150
tlib_abort("Invalid privilege architecture set. Highest supported version is 1.12");
151151
}
152152
cpu->privilege_architecture = privilege_architecture;

arch/riscv/cpu.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -324,6 +324,11 @@ enum privilege_architecture {
324324
RISCV_PRIV1_10,
325325
RISCV_PRIV1_11,
326326
RISCV_PRIV1_12,
327+
// For features that are not yet part of ratified privileged architecture,
328+
// use RISCV_PRIV_UNRATIFIED.
329+
// Replace with an actual version once it becomes a part of ratified spec.
330+
// KEEP LAST
331+
RISCV_PRIV_UNRATIFIED
327332
};
328333

329334
// The enum encodes the fmt field of opcode

arch/riscv/op_helper.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -169,15 +169,16 @@ static target_ulong mtvec_stvec_write_handler(target_ulong val_to_write, char* r
169169
{
170170
target_ulong new_value = 0;
171171

172-
if (((env->privilege_architecture >= RISCV_PRIV1_10 && env->privilege_architecture < RISCV_PRIV1_11) && (val_to_write & 0x2)) ||
172+
bool is_before_clic = env->privilege_architecture < RISCV_PRIV_UNRATIFIED;
173+
if (((env->privilege_architecture >= RISCV_PRIV1_10 && is_before_clic) && (val_to_write & 0x2)) ||
173174
(env->privilege_architecture < RISCV_PRIV1_10 && (val_to_write & 0x3))) {
174175
tlib_printf(LOG_LEVEL_WARNING, "Trying to set unaligned %s: 0x%X, aligning to 4-byte boundary.", register_name, val_to_write);
175176
}
176177

177178
switch (cpu->interrupt_mode)
178179
{
179180
case INTERRUPT_MODE_AUTO:
180-
if (env->privilege_architecture >= RISCV_PRIV1_11) {
181+
if (env->privilege_architecture >= RISCV_PRIV_UNRATIFIED) {
181182
new_value = val_to_write;
182183
} else if (env->privilege_architecture >= RISCV_PRIV1_10) {
183184
new_value = val_to_write & ~0x2;

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