[#59539] riscv: Add CLIC interrupt state

Author: p-woj

arch/riscv/cpu.h

@@ -216,12 +216,17 @@ struct CPUState {
     int32_t pmp_napot_grain;
 
     /* Supported modes:
-         * 0 (INTERRUPT_MODE_AUTO) - chceck mtvec's LSB to detect mode: 0->direct, 1->vectored
+         * 0 (INTERRUPT_MODE_AUTO) - check mtvec's LSB to detect mode: 0->direct, 1->vectored, 3->clic
          * 1 (INTERRUPT_MODE_DIRECT) - all exceptions set pc to mtvec's BASE
          * 2 (INTERRUPT_MODE_VECTORED) - asynchronous interrupts set pc to mtvec's BASE + 4 * cause
      */
     int32_t interrupt_mode;
 
+    int32_t clic_interrupt_pending;
+    uint32_t clic_interrupt_vectored;
+    uint32_t clic_interrupt_level;
+    uint32_t clic_interrupt_priv;
+
     CPU_COMMON
 
     int8_t are_post_opcode_execution_hooks_enabled;

arch/riscv/helper.c

@@ -60,6 +60,10 @@ void cpu_reset(CPUState *env)
     env->mtvec = DEFAULT_MTVEC;
     env->pc = DEFAULT_RSTVEC;
     env->exception_index = EXCP_NONE;
+    env->clic_interrupt_pending = EXCP_NONE;
+    env->clic_interrupt_vectored = 0;
+    env->clic_interrupt_level = 0;
+    env->clic_interrupt_priv = 0;
     set_default_nan_mode(1, &env->fp_status);
     set_default_mstatus();
     env->custom_instructions_count = custom_instructions_count;